1. Field of the Invention
The present invention relates to a plating apparatus and a plating method, and more particularly to a plating apparatus and a plating method used for filling a fine interconnect pattern formed in a substrate, such as a semiconductor wafer, with metal (interconnect material), such as copper, so as to form interconnects.
2. Description of the Related Art
Recently, there has been employed a circuit forming method comprising forming fine recesses for interconnects, such as trenches or via holes in a circuit form, in a semiconductor substrate, embedding the fine recesses with copper (interconnect material) by copper plating, and removing a copper film (plated film) at portions other than the fine recesses by CMP means or the like. In this method, from the viewpoint of reducing loads on subsequent CMP, it is desirable that a copper plated film be deposited selectively in trenches or via holes in a circuit form, and that the amount of copper plated film deposited on portions other than the trenches or via holes be small. In order to achieve such an object, there have heretofore been proposed various ideas regarding a plating solution, such as composition in a bath of a plating solution or a brightener used in a plating solution.
A plating apparatus having the following configuration has been known as this type of plating apparatus used for plating to form fine interconnects having high aspect ratios. A substrate is held in such a state that a surface (surface to be plated) of the substrate faces upward (in a face-up manner). A cathode is brought into contact with a peripheral portion of the substrate so that the surface of the substrate serves as a cathode. An anode is disposed above the substrate. While a region between the substrate and the anode is filled with a plating solution, a plating voltage is applied between the substrate (cathode) and the anode to plate a surface (surface to be plated) of a substrate (for example, see Japanese laid-open patent publication No. 2002-506489).
In a plating apparatus in which a substrate is held and plated in single wafer processing while a surface of the substrate faces upward, a distribution of a plating current can be made more uniform over an entire surface of the substrate to improve uniformity of a plated film over the surface of the substrate. Generally, the substrate is transferred and subjected to various processes in such a state that a surface of the substrate faces upward. Accordingly, it is not necessary to turn the substrate at the time of plating.
Meanwhile, in order to deposit a copper plated film selectively in trenches in a circuit form or the like, there has been known a method of bringing a porous member into contact with a substrate such as a semiconductor wafer, and plating the substrate while relatively moving the porous member in a contact direction (for example, see Japanese laid-open patent publication No. 2000-232078).
In the prior art, however, when plating is performed, the amount of plated material is different in regions of the surface of the substrate depending on the shape of the interconnect pattern, such as trenches and via holes, under the influence of distribution of current density or the influence of additives, and hence it is difficult to form a plated film having a uniform thickness over the entire surface of the substrate. For example, a plated film deposited on an interconnect section having a dense fine interconnect pattern (trenches) is thicker than a plated film deposited on other portions, and a phenomenon called an overplating phenomenon generally occurs. On the other hand, the amount of plated material deposited on an interconnect section having a wide interconnect pattern (trenches) is generally smaller than that on other portions. As a result, in a case where an interconnect pattern is filled entirely with interconnect material such as copper by plating, the thickness of a plated film differs depending on the locations, causing irregularities of the surface of the plated film. When plating is performed according to such method, a greater amount of plated material than necessary is deposited, and hence raw material cost increases and a longer period of plating time is required. Further, loads on a polishing process, such as CMP or the like, after plating increase, and in the next generation in which a low-k material is used as an interlevel dielectric layer, a polishing apparatus will require a considerably high performance. Therefore, it is desirable that the plated film having higher surface flatness is deposited without being affected by variations in the shape of interconnect patterns.
It is desirable to fill up all interconnect patterns (trenches and via holes) uniformly with an interconnect material such as copper or the like, thereby forming interconnects that are free of voids therein. However, it is generally difficult to fill up trenches, particularly for interconnects that are fine and have a high aspect ratio, uniformly with an interconnect material such as copper or the like. It is more difficult to meet the above requirement for depositing a plated film having higher surface flatness without being affected by variations in the shape of interconnect patterns.
In order to solve the above problems, efforts have been made to improve plating solution details such as the composition of a plating bath, a brightener used in the plating solution, etc., and also to improve current conditions. Though these improvements are effective to a certain extent, they are not sufficient to solve the problems, and there are certain limits placed thereon at present.
If finer interconnects are to be formed, then it is preferable to individually perform plating which employs a plating solution suitable for filling finer interconnect patterns and plating which employs a plating solution suitable for reducing overplating. To meet such a need, two plating cells are generally required. Therefore, the plating apparatus not only needs a larger footprint, but also has an increased processing period as it is necessary to transfer substrates between the two cells.